本來以為只有講be ，lo3-lo3-tng5 kong2 一堆

IBM 為大家負重前行

virtually tagged caches - arm

only do aligned memory accesses - mips, arm

expose your pipeline details in the ISA - mips

他說是delay slot，我到覺得是hw 自己搞自己，沒想到OOO 會很難做

extended memory windows - arm

register windows - arm sparc

in fact, require software fallbacks for pretty much anything unusual - 不知 float80 算嘛

- make exceptions asynchronous - 不知

找到一張厲害的圖，但只到1960