[R0] Keynote: 唔,我聽不懂他講的Verilog的口音... 然後VHDL我聽成VGL... (逃)
"Many hardware designers don't want to hear that it's all just software programming." 靠,好婊XDDD
看了MyHDL example,靠,還真的有人這樣玩呀... 除了 @always(clk.positive) 這個比較陌生之外,其他真的是python呀...
不過至少always和clk.positive有一種說不出的熟悉感... XD